FVF LDO regulator with dual dynamic-load composite gain stage

Abstract

A low-voltage output-capacitorless low-dropout regulator using dual dynamic-load composite gain stage for flipped voltage follower topology is presented. It also incorporates a delay discharge circuit which aims to reduce the long discharge time arising from the large capacitive load, thus achieving the overshoot time reduction and sustaining fast transient characteristic when driving low-power digital system with internal heavy capacitive load requirement. The regulator can support a minimum of 0.75 V input voltage with 0.5 V output voltage. It consumes 49.4 µA whilst maintaining the stability for a capacitance load range from 470 pF to 10 nF. For a current load transient from 0 to 10 mA with 200 ps edge time, the settling time is 0.38 µs for the load capacitance of 3 nF. The obtained transient figure-of-merit is 0.42 mV. This transient metric outperforms the representative prior-art reported works.