Future trends in flash memories

Abstract

In recent years, flash memories have become the fastest growing segment of semiconductor memories. According to various analysts, the flash memory market is expected to grow at CAGR of 20%, compared to CAGR of 15% for DRAM and 10% for SRAM during 1996-1998. Some of the key applications driving this growth in flash memories are telecommunications devices, cellular telephones, modems, networking equipment, PC BIOS, disk drives, and set-top boxes. Emerging applications like digital cameras, DTAD, PDAs are also using flash memories for data storage. Further, flash is also finding its place in various new microcontrollers for leading edge embedded applications. Fueled by high volume applications such as cellular telephones, the flash market has grown to about $1.8B in 1995 from $900M in 1994 and is projected to grow to about $2.3B in 1996. Flash memory has indeed carved out a position alongside DRAM and SRAM as a key driver of memory technology. Flash memory began as a modification of the EEPROM with the realization that by erasing the entire EEPROM array at once, a lot of circuitry, including the control transistor in every cell, could be eliminated. Increased demand for flash memory has sparked the advent of numerous new cell structures, design architecture, and manufacturing processes. At present, projects using a hot electron injection based programming/Fowler-Nordheim tunnel based erase, and NOR architecture dominate the marketplace. Other architectures, such as NAND and DiNOR have also emerged. A clear trend toward single supply voltage is emerging, with some vendors offering devices which can work with both dual voltage and single voltage during write/erase operation. With the burgeoning demand for low voltage operation for applications in mobile computing and communications, low voltage and low power flash devices are inevitable. These types of devices will employ low power tunneling mechanisms for both write and erase operation. Thinner tunneling dielectrics, in conjunction with on-chip voltage pumps would be employed to lower the supply voltage requirements. For applications requiring random access, such as code/data storage for cellular phones or PC BIOS, the NOR architecture will continue to dominate. However, for mass storage application where serial access in important, the NANSD architecture will also be a contender. For low density embedded applications, where process simplification may be a higher priority over the cell size, two transistor EEPROM based flash devices will continue to be used. Memory density is primarily driven by mass storage applications. At present 16M flash devices are available, and 64M devices are around the corner. So far, flash memories have lagged one generation behind DRAM in terms of device density. However, with flash memories approaching DRAM like densities, an interesting debate has emerged-will Flash displace DRAM? In fact, ioa7-4852/96$5.00