Abstract
The advancement of bipolar VLSI technology coupled with the lower complexity of RISC (reduced instruction set computer) architectures has made possible bipolar ECL (emitter coupled logic) implementations of single-chip instruction units with much higher clock rates. It is projected that future RISC generations will be implemented in BICMOS as well as ECL and CMOS. It is concluded that ECL-based technology should continue to produce the fastest chips, but the technology must evolve to provide even higher densities and far more on-chip memory to maintain its position
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