Further Study of the U-Shaped Channel SOI-LIGBT With Enhanced Current Density for High-Voltage Monolithic ICs

Abstract

A high-voltage silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT) with U-shaped channels, which are composed of parallel channels and orthogonal channels for improving the current density ( $J_{C}$ ) and latch-up immunity, is proposed and studied intensively in this paper. By using the U-shaped channels, the electron injection from the emitter into the $n$ -drift region is significantly enhanced, and the current density is improved. In addition, an analytical model is proposed, and it is indicated that $J_{C}$ can be improved as $\alpha $ (the angle between the parallel channel and the orthogonal channel) increases in a certain range. The hole current density distribution in the ON-state and the lattice temperature distribution in the short-circuit state of the proposed structure are also investigated. Increasing $\alpha $ is beneficial to alleviate the holes crowding beneath the n+ emitter and suppress the temperature rise in the JFET region, which is favorable for increasing the latch-up voltage ( $V_{\textrm {LP}}$ ) and short-circuit withstand time ( $t_{\textrm {SC}}$ ). The experiments demonstrate that the U-shaped channel SOI-LIGBT fabricated with 0.5- $\mu \text{m}$ SOI technology exhibits a high current density ( $J_{C}$ ) of 305 A/cm2 at $V_{\textrm {CE}}=3$ V and $V_{\textrm {GE}}=5$ V, and a low specific ON-resistance ( $R_{{\mathrm{\scriptscriptstyle ON}}\,\cdot \,\textrm {sp}}$ ) of 0.984 $\Omega \cdot \textrm {mm}^{2}$ with breakdown voltage of 590 V. The improved latch-up voltage ( $V_{\textrm {LP}}$ ) of 560 V and the short-circuit withstand time ( $t_{\textrm {SC}}$ ) of 5.1 $\mu \text{s}$ are obtained.