Abstract
A review is presented of electrical testing, failure mechanisms, fault models, fault simulation, testability analysis, and test-generation methods for CMOS VLSI circuits. The relationships between the most commonly used fault models are explored. Various fault simulation methods are contrasted. The basic mechanisms used in test-vector generation are illustrated by examples. The importance of testability analysis as a guide to design and test generation is discussed. Algorithms for automatic test-pattern generation are summarized. >
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