Fundamentals of Heat Dissipation in 3D IC Packaging and Thermal-Aware Design

Abstract

Cooling of a planar 2D IC chip utilizes heat transfer from a face of the chip though a heat sink. In case of a 3D IC chip stack, the individual chip faces are not available for mounting conventional heat sinks. Mounting the heat sinks on the ends is feasible, but the heat flow paths for the interior chips from the junction to the heat sink become longer. Further, multiple heat sources present along the heat flow paths in stacked chips may create localized hot spots which exceed the allowable junction temperatures. While 2.5D integration in complex ICs where individual layers are mounted on another base die called an interposer can alleviate the heat dissipation issues, it cannot deliver the benefits of monolithic 3D ICs due to the planar distance between the chips or chiplets over the interposer. Introducing interlayer cooling with microchannels and introducing fins in the coolant flow paths extend the thermal dissipation capability of a 3D stack; however this is often accompanied with taller microchannels that lead to longer lengths of through-silicon-vias (TSVs). Placement of TSVs, microchannels walls and fins present conflicting design requirements. Therefore co-design and innovative approaches are seen as critical before widespread commercialization of 3D ICs becomes a reality. An overview of the available cooling options for 3D ICs and their performance evaluation are presented in this chapter.