Fundamental Limits on Run-Time Power Management Algorithms for MPSoCs

Abstract

We consider the case of multiprocessor systems-on-chip (MPSoC) implemented using multiple voltage and frequency islands (VFIs) relying on fine-grained dynamic voltage and frequency scaling (DVFS) to reduce the system power dissipation. We present a framework to theoretically analyze the impact of three important technology driven constraints; (i) reliability-driven upper limits on the maximum supply voltage; (ii) inductive noise-driven constraints on the maximum rate of change of voltage/frequency; and (iii) the impact of manufacturing process variations on the performance of DVFS control for multiple VFI MPSoCs. The proposed analysis is general, in the sense that it is not bound to a specific DVFS control algorithm, but instead focuses on theoretically bounding the performance that any DVFS controller can possibly achieve. Our experimental results on real and synthetic benchmarks show that in the presence of reliability and temperature driven constraints on the maximum frequency and maximum frequency increment, any DVFS control algorithm will lose up to 87% performance in terms of the number of steps required to reach a reference steady state. In addition, increasing process variations can lead to up to 60% of fabricated chips being unable to meet the specified DVFS control specifications, irrespective of the DVFS algorithm used (the material in this paper is based on a prior work by the authors as described in Garg etal., ACM J Emerg Technol Comput Syst (JETC) 8(4):28, 2012; Technology-driven limits on DVFS controllability of multiple voltage-frequency island designs: a system-level perspective. In: Proceedings of the 46th IEEE/ACM design automation conference, San Francisco. IEEE, pp818–821, 2009).