Abstract
The quest for solid state non-volatility memory devices on silicon with high storage density, high speed, low power consumption has attracted intense research on new materials and novel device architectures. Although flash memory dominates in the non-volatile memory market currently, it has drawbacks, such as low operation speed, and limited cycle endurance, which prevents it from becoming the “universal memory”. In this report, we demonstrate ferroelectric tunnel junctions (Pt/BaTiO3/La0.67Sr0.33MnO3) epitaxially grown on silicon substrates. X-ray diffraction spectra and high resolution transmission electron microscope images prove the high epitaxial quality of the single crystal perovskite films grown on silicon. Furthermore, the write speed, data retention and fatigue properties of the device compare favorably with flash memories. The results prove that the silicon-based ferroelectric tunnel junction is a very promising candidate for application in future non-volatile memories.
Highlights
Fabricating ferroelectric tunnel junction (FTJ) on silicon substrates becomes essential for the practical application of FTJs as memories
The downward domain changed into upward domain, which reveals a 180° switching path as shown in Fig. 1 (c)
It has already been reported that a giant tunnelling electroresistance (TER) was achieved by modulating the barrier width using n-type doped Nb:SrTiO3 as bottom electrode through ferroelectric field effect[16]
Summary
Fabricating FTJs on silicon substrates becomes essential for the practical application of FTJs as memories. The non-volatile memory function of FTJs on silicon substrate was demonstrated by using conductive atomic force microscopy (c-AFM)[20]. A real FTJ device demonstration as well as the performances of FTJ devices on silicon substrate such as the writing speed, endurance and fatigue are still lacking and warrant investigation. In this work, we demonstrate epitaxial FTJ devices on Si substrates with BTO tunnel barrier with thickness varying from 1.5 to 4 nm. The dependence of TER on BTO thickness, the writing time, the endurance and fatigue of the FTJs device were investigated. After the deposition of LSMO, an ultrathin layer of BTO was grown as the ferroelectric tunnelling barrier layer. Following the BTO deposition, an array of 5 μ m × 5 μ m Pt electrodes (25 nm thick) was patterned on top for subsequent electrical characterizations
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