Fully-depleted accumulation-mode PMOSFET for 0.2 μm SOI technology

C Raynaud,J.L Pelloie,B Dunne,J Hartmann,O Faynot

doi:10.1109/soi.1995.526436

Fully-depleted accumulation-mode PMOSFET for 0.2 μm SOI technology

C Raynaud, J.L Pelloie + Show 3 more

https://doi.org/10.1109/soi.1995.526436

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Publication Date: Oct 3, 1995

Citations: 1

Affiliation: CEA LETI, CEA Grenoble, Atomic Energy and Alternative Energies Commission

#Fully Depleted Devices #Accumulation-mode PMOSFET + Show 8 more

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Abstract

SOI technology is a promising candidate for low-voltage low-power applications where both partially and fully depleted devices can be used to fulfil the related requirements. One advantage of fully-depleted devices is that a single N+ gate process can be kept for an advanced CMOS process. We show in this paper that an accumulation-mode fully-depleted PMOSFET using an N+ gate can be optimized for a 0.2 /spl mu/m SOI CMOS technology.

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