Abstract
Three-dimensional (3-D) video brings people strong visual perspective experience, but also introduces large data and complexity processing problems. The depth estimation algorithm is especially complex and it is an obstacle for real-time system implementation. Meanwhile, high-resolution depth maps are necessary to provide a good image quality on autostereoscopic displays which deliver stereo content without the need for 3-D glasses. This paper presents a hardware implementation of a full high-definition (HD) depth estimation system that is capable of processing full HD resolution images with a maximum processing speed of 125 fps and a disparity search range of 240 pixels. The proposed field-programmable gate array (FPGA)-based architecture implements a fusion strategy matching algorithm for efficiency design. The system performs with high efficiency and stability by using a full pipeline design, multiresolution processing, synchronizers which avoid clock domain crossing problems, efficient memory management, etc. The implementation can be included in the video systems for live 3-D television applications and can be used as an independent hardware module in low-power integrated applications.
Highlights
By using dense depth information, three-dimensional (3-D) video systems[1] such as 3-D Blue-ray, 3-D television (TV) sets provide stereo video, which has multiple views for different viewers
The initial matching cost calculation includes two parts, respectively, the Hamming distance obtained from the census transformed image and the sum of absolute difference (SAD) value based on the original image
The depth estimation system we proposed, the high-definition depth estimation (HDDE) system is implemented and the stereo vision system based on it is setup for performance evaluation
Summary
By using dense depth information, three-dimensional (3-D) video systems[1] such as 3-D Blue-ray, 3-D television (TV) sets provide stereo video, which has multiple views for different viewers. Jin et al.[8] present an FPGA-based real-time stereo vision system which processes 640 × 480 images with a disparity range of 32 pixels in 230 fps. Researches implement and evaluate variable efficient matching algorithms in order to get a high-performance depth estimation based on hardware design. Considering the analysis above, a high-definition depth estimation (HDDE) system, which is a real-time FPGA implementation, is proposed in this paper. An, and Zhang: Full high-definition real-time depth estimation for three-dimensional video system processing full HD (1920 × 1080) content with a maximum processing speed of 125 fps and a maximum disparity search range of 240 pixels.
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