Abstract
Adders, Multiplexers and other arithmetic circuits have a crucial role in Digital Signal Processing and various real time applications. Among those, Full adder is a central for most of the digital operations that perform subtraction or addition. Major component is Adder with High performance and a power efficient in specific applications. In this paper, the adder with high performance and power efficient are designed using Gate Diffusion Logic which reduces threshold voltage problem. We designed the circuits with minimum power consumption and with high performance efficiency. For the simulation of the circuits Mentor Graphics with 130nm technology is used. The obtained result shows that the proposed designs consume the minimum power when compared to other designs which are taken for the comparison.
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