Design and VLSI Implementation of Pipelined Multiply Accumulate Unit

Abstract

In the majority of the Digital signal processing (DSP) applications, the critical operations usually involve many multiplications and /or accumulations. So, for real time signal processing applications, high throughput multiplier -accumulator (MAC) is always a key element to achieve a high-performance digital signal processing application. In the last few years, the main consideration of MAC design is to enhance its speed. This is because speed and throughput rate are always the concerns of digital signal processing systems. However due to the increase of portable electronic products, low power designs also become another major consideration. This is because, the limited battery energy of these portable products restricts the power consumption of the system. Therefore the main motivation is to investigate various pipelined MAC architectures and circuit and the design techniques which are suitable for the implementation of high through put signal processing algorithms. The goal of this project was to design and VLSI implementation of pipelined MAC for high-speed DSP applications at 180nm technology. For designing the pipelined MAC, various architectures of multipliers and one bit full adders are considered. The static and dynamic one bit full adder was implemented as the basic block. For checking the functionality of the whole system, spice code is written using the HSPICE by defining all the blocks in the circuit as the sub circuits. Then a schematic capture is done using schematic composer from virtuoso starting from bottom level to top level. Finally the layout for the complete MAC is done using virtuoso.