Abstract
28 nm FD-SOI technology is electrically characterized aiming at cryogenic applications. Electrostatics and transport are evaluated and compared while lowering temperature from 300 K down to 4.2 K. Split CV technique is applied in both long and short channel transistors thanks to multiple parallel structures designed to increase the gate area. FD-SOI versatility is shown over a wide temperature range of operation, as the back gate tuning efficiency is preserved at low temperatures. Insights on back gate bias behavior at room and low temperatures are obtained and the electrostatic coupling between front and back channels can be successfully modelled by using 1D Poisson-Schrödinger calculation from 300 K down to 4.2 K. A generic form of empirical models for the effective mobility is found to be useful for cryogenic operation, since the phonon scattering contribution presents strong temperature dependence. While long channel MOSFETs exhibit strong mobility improvement, short channel transistors show lower mobility gain with temperature reduction.
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