From UML diagrams to simulink models

Abstract

The last decade witnessed an enormous increase in the use and complexity of embedded systems. To enable a fast development of these systems while guaranteeing their quality, different kinds of models may be used. UML and Simulink are attractive languages for embedded systems design and modeling that allow to describe systems at different levels of abstraction. An automatic mapping from UML to Simulink is an useful resource in a seamless design flow, allowing designers to use UML as modeling language for the whole system and to use facilities for code generation of Simulink. In previous work, an UML to Simulink translation was formalised using graph grammars and prototyped using a Java implementation. The use of a formal language allowed the verification of important properties of the mapping, like termination and confluence (ensuring, e.g., that there is a unique model resulting from the transformation). In this work, an extension of this formal definition is presented to support nested method calls, reducing restrictions and keeping the compatibility and the properties of termination and confluence of the original translation.