Abstract

Short product cycles and the necessity to achieve a short time to market call for sophisticated design methodologies. In this paper a seamless design flow is described enabling the design of engineering a chip for carrier synchronization of 8PSK, QPSK and BPSK modulated signals in three months. The circuit was fabricated in a 1 /spl mu/m CMOS process using standard cells and is currently in commercial use in a modem for digital TV transmission.

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