From LIF to AdEx neuron models: Accelerated analog 65 nm CMOS implementation

Abstract

Here we present analog circuits emulating an Adaptive Exponential I&F (AdEx) neuron model developed for our second generation 65-nm CMOS neuromorphic hardware. Designed for an existing accelerated Leaky Integrate and Fire (LIF) circuit, the modular circuit architecture allows us to switch between LIF and AdEx neuron models and further to multiple-compartments. We describe our circuit implementation and the simulation results for adaptation and exponential sub-circuits. The neuron circuit specifications are compared with a targeted set of computational models. We show how addition of analog AdEx circuits let us qualitatively reproduce spike patterns known from cortical neurons.