From bulk toward FDSOI and silicon nanowire transistors: Challenges and opportunities

Abstract

The silicon MOS transistors for VLSI have been scaled down for more than forty years in order to attain higher speed, lower power, higher integration, and lower cost. The gate length is now less than 30 nm. The silicon devices are certainly in the nanometer regime. Fig. 1 shows technology nodes and gate length according to ITRS [1]. It is predicted in the 2009 version of ITRS that the gate length will become less than 10 nm in 2021 in production. In the research level, a CMOS device with 3.8nm gate length has already been reported [2]. However, there are a lot of technical barriers to realize the 10nm-scale CMOS devices. It is now well recognized that simple scaling of bulk MOSFETs will fail in the nanometer regime. Every effort to extend the CMOS platform to future information technologies is being made. In this talk, transistor evolution for further CMOS extension is presented. Conventional planar bulk MOSFETs are compared with emerging fully-depleted SOI MOSFETs and nanowire MOSFETs in terms of short channel effects, carrier transport, and variability, and the advantages of new channel structures are discussed.