From algorithm to VLSI for HDTV

Abstract

A fully integrated video design environment will be used to design an experimental chip set for the bandwidth restoration decoder (BRD), which is part of the European HDTV transmission system called HDMAC. This chip-set development and the chip design system are described. A powerful property of the system is that the testability of the design can be guaranteed by integrating powerful test tools in the design flow. Combining a video simulator with a chip design system allows hierarchical design flow with less risk of functional errors and shortens the throughput times from algorithm development to chip and system evaluation. >