Abstract

At the heart of each frequency modulated continuous wave (FMCW) radar system lies the synthesizer. Its task is the generation of the waveform for distance and/ or velocity measurements with the system. The performance characteristics of this component have a direct impact on key performance criteria of the radar system, such as measurement speed and accuracy. A number of different synthesizer concepts exist in the literature [1] . Nowadays the most popular concepts rely on a phased-locked loop (PLL) for the generation of the radar chirp. Two different PLL-based synthesizer solutions exist today. One is based on an Integer-N PLL and a direct digital synthesizer (DDS). In this concept the DDS acts as a reference oscillator for the PLL and the chirp is generated at the reference frequency. The task of the PLL is then to multiply the frequency by its division factor N to the high output frequency. The output frequency is a fixed multiple of the reference frequency. The other solution is the usage of a fractional-N PLL. In this concept the reference frequency is fixed and the division value of the frequency divider is variable. Normally the step size of the output frequency would be limited to the reference frequency. However with a continuous switching of the divider value any fractional value can be generated for the division ratio. Early fractional-N PLL used a regular pattern of divider values generated with a fractional accumulator. This however leads to additional spurs in the output spectrum. An improved version of a fractional-N PLL uses a ΔΣ modulator to mitigate this effect. The fractional-N PLL is superior to the integer-N approach. On the one hand the power consumption is significantly reduced. Instead of a power-hungry DDS, often using more than 100mW, only a ΔΣ modulator with a power consumption of around 1mW is necessary. On the other hand also the chip area and thus the costs for the system are reduced.

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