Frame-by-frame speech recognition as hardware decoding on FPGA devices

Masashi Nakayama,Shunsuke Ishimitsu,Naoki Shigekawa,Takashi Yokouchi

doi:10.1109/icsenst.2015.7438503

Frame-by-frame speech recognition as hardware decoding on FPGA devices

Masashi Nakayama, Shunsuke Ishimitsu + Show 2 more

https://doi.org/10.1109/icsenst.2015.7438503

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Publication Date: Dec 1, 2015

Citations: 4

Affiliation: Hiroshima City University, University of Fukui, National Institute of Technology, Kagawa College

#Field Programmable Gate Arrays Devices #Field Programmable Gate Arrays + Show 8 more

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Abstract

This paper proposes frame-by-frame speech recognition as a hardware decoder on Field Programmable Gate Arrays (FPGAs). As a first step for FPGA implementation, Voice Activity Detection (VAD) using second order autocorrelation and a speech recognition decoder using formant frequency distances were evaluated. The hardware decoding was then implemented on an FPGA emulator. The VAD and decoder were demonstrated to be effective, and hence could be suitable for implementation on FPGA devices.

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