Frame-by-Frame Speech Signal Processing and Recognition for FPGA Devices

Abstract

This paper discusses and experiments on frame-by-frame speech signal processing and recognition for Field Programmable Gate Array (FPGA) devices. The system proposes applications including a voice conversion system that needs signal processing and speech recognition for each frame because it requires real-time processing at each frame. Owing to the processing speed, the authors propose algorithms for FPGA as a hardware processor for Voice Activity Detection (VAD) and speech recognition decoder. However, resources for FPGA devices as gate circuits are minimal, therefore, the algorithms need to be customized in order to implement the FPGA. The algorithms are customized for VAD using a 2nd-order autocorrelation function, and for speech recognition using Euclidian distance. These methods implement an FPGA emulator that demonstrates VAD of speech and noise sections and a speech recognition experiment for discriminating Japanese vowels.