F-PLD data retention times and test methods

Abstract

Data retention times in Non-Volatile Memory (NVM) components are an issue that is pervasive throughout industry, but left unaddressed due to product life cycles, typically, being significantly under the retention time or as is often the case the data on the NVM component is simply refreshed when a problem arises. In this paper we outline the initial process and testing method being developed to better determine the data retention time of NVM components. One goal of this effort is to obtain a data retention time using a black box approach i.e. no need to get inside the chip. Measurements on the test chip show that the basic method allows detection and measurement of the voltage at which the output value flips on at least 200 bits per chip, most with about 1mV accuracy — least for the test chipset. By measuring the change in these voltages over time we measure leak rates. By comparing leak rates to various other parameters we are able to process the data to obtain data retention times. With sufficiently sensitive equipment we can do this at room temperature. Test results show high leak rates and other related issues that tend to confirm that: (1) data retention times in NVM are an issue, (2) the standard test methods need update, and (3) that new methods can test the chips directly at room temperature, avoiding the need for temperature extrapolation.