FPGA-Based Hardware Modeling on Pigeon-Inspired Optimization Algorithm

Abstract

AbstractBy learning behavioral characteristics and biological phenomena in nature, such as birds, ants, and fireflies, intelligent optimization algorithms (IOA) is proposed. IOA shows feasibility in solving complex optimization problems in reality. Pigeon-inspired optimization (PIO) algorithm, which belongs to intelligent optimization algorithms, is proposed by the pigeons homing navigation behavior inspired. PIO is superior to other algorithms in dealing with many optimization problems. However, the performance of PIO processing large-scale complex optimization problems is poor and the execution time is long. Population-based optimization algorithms (such as PIO) can be optimized by parallel processing, which enables PIO to be implemented in hardware for improving execution times. This paper proposes a hardware modeling method of PIO based on FPGA. The method focuses on the parallelism of multi-individuals and multi-dimensions in pigeon population. For further acceleration, this work uses parallel bubble sort algorithm and multiply-and-accumulator (MAC) pipeline design. The simulation result shows that the implementation of PIO based on FPGA can effectively improve the computing capability of PIO and deal with complex practical problems.KeywordsIntelligent optimization algorithmPigeon-inspired optimizationFPGA