FPGA-Based Efficient Implementation of CBNS Computational Circuits: A Modular Approach

Abstract

Abstract Complex binary number system (CBNS) finds extensive applications in the faster computation of various digital signal processing (DSP) algorithms. In this paper, an attempt has been undertaken to develop various computational circuits based on CBNS for implementation in Spartan XC3S700A FPGA platform. The circuits have been designed following a modular approach. The designed modules involve simple logic gates leading ultimately to efficient implementation on FPGA. The codes for the modules have been developed using verilog hardware description language (HDL). Structural-level designs of nibble size CBNS adder, multiplier, and subtractor have been exclusively accomplished involving these modules. In the design of multiplier and subtractor, a new concept of sub-block has been introduced to efficiently utilize the limited input capability of the designed modules. The proposed design involves less hardware complexity, silicon area, and path delay compared to existing works. Simulation results and performance metrics for all the three CBNS circuits have been included.KeywordsCBNSFPGAModular approachNibble sizeConceptual approach