Utilization of DSP algorithms for Cyclic Redundancy Checking (CRC) in Controller Area Network (CAN) controller

Abstract

Controller Area Network (CAN) controller is an integral part of Electronic Control Unit (ECU) particularly in Advanced Driver Assistance System (ADAS) application, its characteristics should always be advantageous in all aspects of functionality. Primarily, the costing should be low but maintaining the reliability of this technology. However, CAN protocol is implementing serial operation resulting to a slow throughput. In this paper, we utilized the Digital Signal Processing (DSP) algorithms, namely pipelining, unfolding and retiming to CAN controller in Cyclic Redundancy Checking (CRC) unit particularly for Encoder and Decoder section in able to attain the feasible iteration bound, critical path that is appropriate for CAN system and to obtain superior design of a high speed parallel circuit for CRC. The source code for Encoder and Decoder has been formulated in Verilog Hardware Description Language (HDL).