FPGA-based digit-serial complex number multiplier-accumulator

Abstract

This paper presents a FPGA implementation of digit-serial complex number Multiplier-Accumulators (CMACs) based on Booth recoding techniques and carry save (CS) adders. The complex number Multiplier-Accumulators can be pipelined at LUT-level. An efficient mapping of the Booth recoding and the partial product generation is presented which results in a logic depth reduction. The combination of 5-3 and 4-3 converters in the CS structure and the utilization of ripple carry adder (RCA) trees lead to a minimum area requirement.