FPGA modeling of a novel fully-synthesizable and secure TRNG based on key-dependent s-box

Abstract

In this study, the Field Programmable Gate Array (FPGA) implementation of a True Random Number Generator (TRNG) using dynamic key-based s-box architecture as a post-processing technique is presented. In the proposed architecture, the post-processing method of TRNG consists of two different functions, in a total of 32x32 (32-bit input & 32-bit output), containing four independent 8x8 (8-bit input & 8-bit output) s-boxes. Raw random numbers are subjected to three-stage substitution operations in these functions, and their statistical properties are cryptographically improved. The post-processing unit of TRNG is compressionless as the s-boxes are 8 x 8. Thanks to this distinctive feature of the proposed method, TRNG can reach a final output bit rate of 250 Mbps with an entropy of 0.99. With the same output bit rate, TRNG passes the National Institute of Standard and Technology (NIST) Special Publication (SP) 800-22 statistical randomness evaluation tests with success above the minimum confidence interval of 0.9805. In addition to the NIST tests, bias, entropy, correlation, chi-square, and true randomness analyses are also given for TRNG's cryptographic verification. Besides to the statistical requirements, cost and performance analyses for TRNG are also presented in the study. The estimated dynamic power consumption for TRNG needing a low chip area of 2% (3221 LEs) for hardware implementation, is measured as 10.2 mW. The final results show that TRNG has high security and efficiency standards and can be used successfully in embedded cryptographic applications.