FPGA Implementations of Ladder Diagrams

Neil William Bergmann,Sunil K Shukla,Peter Waldeck

doi:10.5539/mas.v7n3p64

Abstract

The performance of programmable logic controllers is often constrained by the microprocessor and the real-time firmware of the controller. Field programmable gate arrays (FPGAs) are an attractive potential implementation medium for high-speed control because of their fast and parallel execution and programmable nature. Ladder Diagrams are a standard graphical programming method for industrial controllers, but compilers from Ladder Diagrams to FPGA hardware do not yet exist. This paper explores the comparative speed of four different classes of FGPA implementation of Ladder Diagrams - Interpreted Software, Compiled Software, Interpreted Hardware and Compiled Hardware. It also explores parallel versus serial execution of Ladder Diagrams in hardware, and identifies timers as a major resource user in parallel implementations. Overall, a Shared Timer Serial Compiled Hardware system for FPGA implementation of Ladder Diagrams is recommended. Using comparable FPGA resources to other alternatives it provides a 20-600 times speed improvement over other solutions whilst maintaining correct Ladder Diagram semantics.

Highlights

Before the introduction of programmable controllers, relays were commonly used to implement control systems
There has been little published on the direct implementation of Ladder Diagrams control algorithms in Field programmable gate arrays (FPGAs), and so this paper undertakes an initial investigation into the advantages and disadvantages of FPGA-based implementations
We investigate an example Ladder Diagrams (LD) application, which uses logic and timers, and investigate different methods for implementing the LD on an FPGA

Summary

Introduction

Before the introduction of programmable controllers, relays were commonly used to implement control systems. With the advent of low-cost microprocessors, Programmable Logic Controllers (PLCs) replaced relays as the predominant control element (Bolton, 2009) As part of their heritage as relay replacements, PLCs are often programmed using a technique originally designed for relay networks - Ladder Diagrams (LD). There has been little published on the direct implementation of Ladder Diagrams control algorithms in FPGAs, and so this paper undertakes an initial investigation into the advantages and disadvantages of FPGA-based implementations.

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Conclusion