Study on LD-VHDL conversion for FPGA-based PLC implementation

Abstract

Programmable logic controllers (PLCs) have been widely used in manufacturing systems for many years. PLC performance is highly constrained by speed of the microprocessor and real-time firmware of the PLC. To enhance conventional PLC performance and flexibility, this paper proposes a new PLC design based on field programmable gate array (FPGA) with parallel execution mechanism and reconfigurable hardware structure. Since ladder diagrams (LD) are the most popular programming language of PLCs, the essential approach of this research is to convert LD programs to equivalent and very high speed integrated circuit hardware description language programs (VHDL), which are the major programming language for FPGA design. This conversion process requires two steps. The first step is to convert the LD program to a VHDL program, in which the LD sequence is controlled by a state machine process. The second step is to optimize the state machine process with concurrent sensitive signals to assure that independent operations in the LD program can be executed in parallel in FPGA. Considering the diversity of LD instructions from different PLC providers, a universal converter with an extended Boolean equation as a bridge is introduced to implement the conversion of LD programs to VHDL. In the second step, the condensed simultaneity graph theory (CSG) is applied to optimize the converted VHDL program with concurrent sensitive signals, which is explained by a practical example.