FPGA IMPLEMENTATION OF VARIOUS LINES CODING TECHNIQUE FOR EFFICIENT TRANSMISSION OF DIGITAL DATA IN COMMUNICATION

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This paper describes the implementation of various line coding schemes using VHDL on Xilinx Spartans-6 XC6SLX45 FPGA platform for the purpose of security, area optimization and can support efficient digital communication in varying channel environment. The choice of line code depends upon presence or absence of DC level, power spectral density, Bandwidth requirement, Bit error rate (BER) performance, ease of clock signal recovery and presence or absence of inherent error detection property. The line encoding schemes used are Unipolar RZ and NRZ, Polar RZ and NRZ, AMI and Manchester coding and Pseudo ternary encoding, Coded Mark Inversion format. Select pin impinged on the chip enables the users to select any one of the line encoding technique according to their requirement. The modeling and simulation of various line codes are implemented on Xilinx design tools and Hardware abstraction completed on Spartan-6 FPGA.