FPGA Implementation of RSA Encryption Algorithm for E-passport Application

Khaled Shehata,Hanady Hussien,Sara Yehia

doi:10.21608/iceeng.2014.30363

Abstract

Securing the data stored on E-passport is a very important issue. RSA encryption algorithm is suitable for such application with low data size. In this paper the design and implementation of 1024 bit-key RSA encryption and decryption module on an FPGA is presented. The module is verified through comparing the result with that obtained from MATLAB tools. Thedesign runs at a frequency of 36.3 MHz on Virtex-5 Xilinx FPGA. The key size is designed to be 1024-bit to achieve high security for the passport information. The whole design is achieved through VHDL design entry which makes it a portable design and can be directed to any hardware platform.

Highlights

E-passport is a passport that includes a smart card embedded in the back
The International Civil Aviation Organization (ICAO) created sets of e-passport standard [2, 3]. 1024-bit RSA is one of the recommended algorithms used for Active Authentication (AA) protocol
As a result the modular operations for 1024 bits or higher make RSA is difficult to achieve a high throughput. To address this problem many algorithms are invented such as add and shift, Montgomery multiplication and carry save adder (CSA) [High speed rsa 2]. [6,7]

Summary

Introduction

E-passport is a passport that includes a smart card embedded in the back. This card contains the traveler’s personal data. 1024-bit RSA is one of the recommended algorithms used for Active Authentication (AA) protocol. This protocol is used to prevent e-passport cloning [4]. As a result the modular operations for 1024 bits or higher make RSA is difficult to achieve a high throughput. To address this problem many algorithms are invented such as add and shift, Montgomery multiplication and carry save adder (CSA) [High speed rsa 2]. This paper presents the implementation of RSA encryption/decryption algorithm with 1024-bit key length on FPGA. The modular multiplier is implemented using add and shift algorithm presented.

RSA Algorithm

CONCLUSION