Abstract

In this work, the architecture and modeling of two different RSA encryption and decryption public key systems are presented, for a key size of 128 bits. The systems that require different levels of security can be utilized easily by changing the key size. Two different architectures are proposed with and without MMM42 multiplier to check the suitability for implementation in Wireless Sensor Nodes to utilize the same in Wireless Sensor Networks. Synthesis and simulation of VHDL code is performed using Xilinx-ISE for both the architectures. Architectures are related in terms of area and time. The RSA encryption and decryption algorithm implemented on FPGA with data and key size of 128 bits, without modified MMM42 multiplier gives good result with 50% less utilization of hardware. As device utilization is less in the second architecture, the key size can be increased to have more security with good speed for Wireless Sensor Networks.

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