Abstract
The article discusses counters defined in the IEC 61131-3 standard. The possible implementations of standard counters function blocks in FPGAs are presented. First, counters are implemented as classical hardware-based modules. Second, counters are designed as the FPGA built-in memory blocks with a single common executing unit. These solutions are compared to each other and compared with counters realized in commercially available PLCs like Siemens SIMATIC S7 controllers. The structure of integrated hardware–software CPU with counters is presented. The paper presents how the designer can take advantage of the specific features of the FPGA devices to optimize both the utilization of resources and speed of realization of the particular blocks. Experimental results prove the high efficiency of the proposed solutions.
Highlights
IEC 61131 is the international standard for programmable logic controllers (PLCs)
After implementation of each solution, a comparison was made between field programmable gate arrays (FPGAs) resources utilization, as well as the determined maximum clock frequencies
Different units were tested in order to compare counters in ready-made PLCs with presented in the paper solutions
Summary
IEC 61131 is the international standard for programmable logic controllers (PLCs). The third part of this standard is focused on the basic software architecture with programming languages [1]. This is especially important in the era of Industry 4.0, where the smart technology integration requires significantly increased system performance. The fast counters may be implemented in FPGA logic devices as separate modules or can be integrated with CPU in a form of integrated hardware-software PLC. Implementation of a counter needs mapping of a suitable data structure in the controller memory to enable storage of the current content of the counter as well as the status of the PV input and the status of QU and QD outputs.
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