Abstract
The paper introduces new implementation methods of the fuzzy interpreted Petri net (FIPN) on FPGAs. The realization of FIPN is based on fast array multipliers and multipliers utilizing DSP blocks available on FPGA systems. The paper contains descriptions of particular network components' architectures and results of simulations of these components. In the paper a real control system is designed, which is used to show properties of FIPN. A few slightly different implementations of the example control system as well as their comparison in terms of FPGA resources requirement and calculations speed are also featured. The conducted experiments revealed that the proposed FPGA implementation is many times faster than software realizations of the same control system exercising typical microprocessors and microcontrollers.
Highlights
High demands are placed on modern solutions for control systems modeling of practical industrial processes regarding their abilities to deal with complex problems while optimizing the performance of these approaches in terms of the use of hardware resources
FPGA systems are used with success in real-life models, which require implementation of neural networks [1], [2], fuzzy logic algorithms [3], [4] or Petri nets [5], [6]
The second direction focuses on low-level Petri nets, which main applications are centered around programming of industrial controllers or reconfigurable hardware
Summary
High demands are placed on modern solutions for control systems modeling of practical industrial processes regarding their abilities to deal with complex problems while optimizing the performance of these approaches in terms of the use of hardware resources. An interesting and efficient tool, combining Petri nets and fuzzy logic and allowing for effective analysis of modeled systems in terms of their performance and structure, is Fuzzy Interpreted Petri Net (FIPN) introduced in [13] For this net, transitions have conditions assigned to them and their fulfillment is reliant on variables of the simulated system. The proposed idea of hardware implementation of the FIPN, coming from [13], relies on the utilization of fuzzy RS flip-flops and fuzzy gates based on sum and limited multiplication operations These components are costly to implement in FPGAs, have relatively high resources requirement and the overall calculations speed of the FIPN is rather low. Taking advantage of the developed practical example of a control system, a speed comparison between FPGA and software implementations of the FIPN is presented in the paper
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