FPGA Implementation of Compensation Algorithm for Impacts of Eliminated Flicker Noise in Zero IF Architecture PCRs

Abstract

The demand for Vital sign detection in Military Surveillance purposes and Healthcare monitoring purposes has been rising largely thereby making enhancements in RADAR performances imperative. Flicker noise tends to influence the performance of Zero-IF architectures highly. Use of Pre-Defined Filters for Flicker noise elimination causes degradation in radar performance due to elimination of useful low frequencies along with the noise frequencies. The degradation can be improved by introducing an error compensation algorithm which accounts for the eliminated frequencies. In this paper we propose an efficient synthesizable hardware implementation of the compensation algorithm based on a practical Pre-Defined Filter. The Pre-Defined Filter along with the Compensation Hardware can replace the traditional LPFs thereby enhancing RADAR performances.