Abstract
This paper presents a Field Programmable Gate Array (FPGA) implementation for video compression using a Block Truncation Coding (BTC) image compression technique. The implementation exploits the inherent parallelism of the BTC algorithm to provide efficient algorithm-to-architecture mapping. The Xilinx VirtexE BTC implementation has shown to provide 20.5 /spl times/ 10/sup 6/ of pixels per second, which is about 3000 times faster than an Intel Pentium III 550 MHz processor.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
