Abstract
This paper presents a field programmable gate array (FPGA) implementation for video compression using block truncation coding (BTC) image compression technique [E. Delp et al., 1979]. The implementation exploits the inherent parallelism of the BTC algorithm to provide efficient algorithm-to-architecture mapping. The implementation is shown for gray scale images and promoted to color ones. The Xilinx VirtexE BTC implementation has shown to provide about 23.4 /spl times/ 10/sup 6/ of pixels per second which is about 3500 times faster than an Intel Pentium III 550 MHz processor.
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