FPGA Implementation of an Improved Reconfigurable FSMIM Architecture Using Logarithmic Barrier Function Based Gradient Descent Approach

Nitish Das,Aruna Priya P

doi:10.1155/2019/3727254

Abstract

Recently, the Reconfigurable FSM has drawn the attention of the researchers for multistage signal processing applications. The optimal synthesis of Reconfigurable finite state machine with input multiplexing (Reconfigurable FSMIM) architecture is done by the iterative greedy heuristic based Hungarian algorithm (IGHA). The major problem concerning IGHA is the disintegration of a state encoding technique. This paper proposes the integration of IGHA with the state assignment using logarithmic barrier function based gradient descent approach to reduce the hardware consumption of Reconfigurable FSMIM. Experiments have been performed using MCNC FSM benchmarks which illustrate a significant area and speed improvement over other architectures during field programmable gate array (FPGA) implementation.

Highlights

Digital signal processing (DSP) [1,2,3], pattern matching [4], and circuit testing [5] are the primary applications for most of the digital systems
Its inputs are multiplexed to make it hardware oriented, which is known as the finite state machine with input multiplexing (FSMIM)
Its implementation is performed on field programmable gate array (FPGA) platforms [6]

Summary

Introduction

Digital signal processing (DSP) [1,2,3], pattern matching [4], and circuit testing [5] are the primary applications for most of the digital systems. These applications require a hardwareoriented as well as high-speed control unit. Its inputs are multiplexed to make it hardware oriented, which is known as the finite state machine with input multiplexing (FSMIM). It serves as a control unit, and its operating speed determines the processing speed of the system. Its implementation is performed on field programmable gate array (FPGA) platforms [6]

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Methods

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Conclusion