FPGA implementation of an IIR temporal filtering technique for real-time stimulus artifact rejection

Abstract

This paper presents a field-programmable gate array (FPGA) implementation of an infinite impulse response (IIR) temporal filtering technique for real-time stimulus artifact rejection (SAR) with applicability to neuroscience and neural engineering scenarios in which electrical stimulation of the nervous system and recording of neural activity occur in the same medium. Specifically, a digital signal processing (DSP) unit comprising a first-order, IIR, highpass filter followed by the SAR algorithm circuitry and associated timing and operation control unit is synthesized and mapped onto the DE2 Development and Educational Board with the Cyclone II device as its FPGA platform. Using two sets of neural data prerecorded from an Aplysia californica, we first demonstrate that the FPGA simulation results match those obtained with MATLAB™ simulation. Further, measured results from the FPGA verify that memory initialization with the first recorded artifact can speed up the IIR system operation significantly, and that the proposed architecture can eliminate virtually all stimulus artifacts from the recorded data in real time and recover the extracellular neural activity.