FPGA implementation of an 8-bit AES architecture: A rolled and masked S-Box approach

Abstract

As network technology advances, information security issues increase the need for developing low-area and low-power high performance real-time processing of cryptographic algorithms. In this paper, we present a novel 8-bit architecture for Advanced Encryption Standard (AES) encryption which supports keys of 128-bit in length. The proposed architecture consists of a single round of ShiftRows, ByteSubstitution, MixColumns and AddRoundKey operations through which the data is iterated for ten rounds, which results in substantial reduction in terms of area and power consumption. We have proposed a new architecture for ByteSubstitution and AddRoundKey operations by employing high order masking and a different key expansion algorithm respectively, hence making the proposed architecture less vulnerable to Differential Power Analysis (DPA) and saturation attacks. Moreover, we have also utilized a new architecture for ShiftRows operation for further minimizing the area on chip. The proposed architecture was implemented on Virtex-7 FPGA using two different implementation strategies-Performance Explore and Area Explore using Vivado Design Suite. Using performance explore strategy, the proposed architecture worked at the maximum frequency of 200.32 MHz with a throughput of 160.26 Mbps, whereas, with area explore strategy, the proposed architecture utilized 662 slices, 796 LUTs and 0.303 Watt in power.