FPGA implementation of an 8-bit AES architecture: A pipelined and masked approach

Abstract

In accordance with the past trend of technological advancements in hardware implementation of security mechanisms, there is an ongoing decrease in size of cryptographic systems with increase in low power and high throughput constraints. In this paper, we present a novel 8-bit pipelined architecture for Advanced Encryption Standard (AES) which ensures high throughput with low area and power consumption. The proposed architecture supports 10 rounds of encryption, where each round consists ShiftRows, ByteSubstitution, MixColumns and AddRoundKey operations. We have employed boolean masking for all AES operations to increase the security of the intermediate data between the operations and the rounds. To increase the resistance against Differential Power Analysis (DPA) and saturation attacks, high order masking and a different key expansion algorithm in ByteSubstitution and for computing round keys in AddRoundKey operation has been employed respectively. The proposed architecture was implemented on Virtex-7 FPGA using two different implementation strategies: Performance Explore and Area Explore using Vivado Design Suite. Using performance explore strategy, the proposed architecture worked at the maximum frequency of 175.1 MHz with a throughput of 1400.8 Mbps, whereas, while using the area explore strategy, the proposed architecture utilized 7227 slices, 8709 LUTs and 0.717 Watt in power.