Abstract
Adaptive decimation is a technique that can be applied to compress images with good visual quality at low bit-rate. Despite the low complexity of the method, the encoding process involves floating point computation that requires the use of medium speed processors in order to achieve real time operation. In this paper, a new approach has been taken to restructure the adaptive decimation algorithm to a form that includes only small amount of arithmetic operations. The revised algorithm can be implemented with simple logic circuits. The encoder is practically free from complicated numerical computation. A FPGA implementation of the proposed algorithm was realized. The architecture of the encoder is simple and suitable for valuable applications in the development of low cost non-processor based multimedia products.
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