Abstract
A modified algorithm for two-dimensional TPC decoding is proposed to reduce the wrong frame rate in the (16,11,4) <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> Turbo Product Code (TPC) decoding in this paper. It is based on the hard decision decoding, including a chooser and a parallel decoding architecture that one is column-row and the other is row-column. The Monte-Carlo simulation shows that 30% wrong frame is eliminated and the implementation of the decoder for TPC (16,11,4) <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with FPGA has achieved the decoding throughput of 53 Mbit/s with 20 M clock.
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