A Parallel Turbo Product Codes Decoder Based on Graphics Processing Units

Abstract

Turbo product codes (TPC) are a class of forward error correction (FEC) codes. They have good bit error rate (BER) performance at high code rate. It is relatively simple to implement the encoder of TPC and the decoding complexity of their decoder is reasonable. Therefore, TPC are widely used in various places such as satellite communication systems and data storage systems. In this paper, a parallel TPC decoder based on GPUs is proposed. All rows or columns of the two-dimensional product code matrix are decoded simultaneously in this proposed decoder. A parallel elementary decoder is designed to simplify the decoding process of TPC which are constructed by extended Hamming codes. The calculations of test patterns and valid codewords are parallelled to reduce decoding latency. In order to further improve the decoding throughput, we present the multi-channels TPC decoder. The performance of the parallel decoder is measured on different GPUs. The experiment result shows that the decoding latency is reduced significantly compared with the TPC decoder based on a CPU. In addition, throughputs of proposed GPU decoder achieve 30Mbps on Nvidia RTX 2080 Ti and 38 Mbps on Nvidia Titan V, which are 44 times and 54 times of the CPU-based decoder.