Abstract
In this paper, we present the design and implementation on field programmable gate array (FPGA) of a memory-reduced Turbo decoder in the LTE-Advanced standard. By inserting a reverse recalculation module in the conventional Turbo decoding architecture, the state metric cache (SMC) capacity is reduced by 50%. The power estimation demonstrates that, compared with the conventional Turbo decoder, the overall power dissipation of the proposed decoding architecture is decreased by 24%, 29.7% and 31% at the operating frequency of 50MHz, 75MHz and 100MHz, respectively. In addition, the decoding performance is very close to that of the optimal Log-MAP algorithm.
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