Abstract
One Major modeling primitive in the field of Computer Graphics is a planar polygon. This polygon can have an arbitrary number of vertices and different shapes. In this paper a graphic sub-system is designed and implemented using Field Programmable Gate Array ( FPGA ). One of the main tasks of the hardware designed is scan-converting convex planar polygons required to update an image in the image memory or video RAM which is used as a Frame Buffer. A facility to read the pixels (Picture Elements), from the frame buffer, for display on the monitor of the computer is also included in the design. Keywords: frame buffer, scan-conversion, polygons, pixels, FPGA
Highlights
One of the main effective means for communication is the picture
Some of the most sophisticated computer graphics systems are those being used for producing video images in real time
The scan conversion produces pixels which are stored in the frame buffer from which they are taken, using read cycles, for display [3]
Summary
The arithmetic section of the implemented graphic controller searches the polygon vertices to determine the smallest y coordinate and compute the slope of each polygon edge connecting this vertex to the preceding and succeeding ones. From these slopes the graphic controller determines the intersections of each scan line with the polygon edges which in turn define the beginning and end of each span. The graphic controller computes the corresponding address value of the frame buffer using x, and y coordinates. Figure (4) shows a block diagram of the designed graphic controller
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