Fpga Controlled Cascaded Mli With Advanced Multilevel Strategies For Harmonic Reduction

Abstract

This paper focused on the implementation of Cascaded H-bridge multilevel inverter fed induction motor by using the modulating technique of OVPWM with U-type carrier to the Five-level inverter. The PWM switching signals based on offset voltage injected in sine reference with U-type carrier been generated. The multilevel inverter fed induction motor drive with SPWM and proposed strategies are performed and results are analyzed. Xilinx FPGA is a programmable logic device developed by Xilinx, which is considered as an efficient hardware for rapid prototyping. In addition to Xilinx FPGA, MATLAB/Simulink software was used for simulation and verification of the proposed circuit before implementation. Hardware is implemented for a single phase cascaded five level inverter with the proposed modulating technique by using FPGA ,which drives a single phase induction motor of 0.5 H.P Simulation results and hardware results are compared. It is justified that the proposed modulation technique can be recommended to three phase five level Cascaded H-bridge inverter fed three phase induction motor for better performance with reduced harmonics at output. Index Terms- Multilevel concept, Cascade Multilevel inverter, FPGA, Multi level carrier signals, Pulse width modulation, Total Harmonic Distortion. I. INTRODUCTION Modulation in multilevel inverters has recently been widely investigated, but the overvoltage caused by multilevel modulation has not been discussed thoroughly. Several modulation methods, such as space vector pulse width modulation (SVPWM), space vector control (SVC), duty cycle modulation (DCM) and several sine- triangle comparison modulation variations have been presented, for example, in the literature given by Wei.S et.al.(19) and Naumanen et.al.(24). All the modulation methods, except for the SVC, are based on pulse width modulation.. The output voltage waveform of the SVC resembles staircase that approximates the shape of the reference wave. An example of a multilevel inverter using SVC is presented by Kouro.S et.al. (22). Power electronic switches, especially IGBTs have become faster in terms of turn-on and turn-off times, which has led to the high dv/dt of the edges of the PWM voltage. The short rise time compared with the propagation delay causes an oscillating overvoltage at the motor terminals. The propagation delay is caused by the length and insulation of the cable, and with the impedance a mismatch between the cable and the motor an overvoltage occurs. As dv/dt becomes higher, an overvoltage will occur at even shorter cable lengths. This phenomenon has been thoroughly reported by Persson et.al.(6) and Skibinski(9). The classification of PWM techniques or modulating techniques can be classified as shown in Fig.1. Wang et.al (15) in his investigation on sine triangle modulation technique stated that SPWM is the most commonly used modulating technique suffers from certain drawbacks like low fundamental output voltage. The Modified Reference Modulation techniques that offer improved performances as discussed by M.H.Rashid (20) and are as Trapezoidal ,Stair case ,Stepped , Harmonic injected, Space Vector PWM (SVPWM) and Offset voltage injected in reference(OVPWM) The above PWM techniques are applicable to three-phase inverters. However the last three techniques are commonly used for three-phase inverters.