FPGA based High Speed Double Precision Floating Point Divider

Abstract

Floating point arithmetic is widely used in many areas, especially scientific computation and signal processing. For many signal processing, and graphics applications, it is acceptable to trade off some accuracy (in the least significant bit positions) for faster and better implementations. Division is the third basic operation of arithmetic. However, most of these modern applications need higher frequency or low latency of operations with minimal area occupancy. In this paper we describe an implementation of high speed IEEE 754 double precision floating point divider using digit recurrence algorithm and targeted for Xilinx Virtex-6 Field Programmable Gate Array. Verilog is used to implement the design. The implemented design achieves 344.89 MFlops and this design occupies 653 slices. It handles the overflow, underflow and rounding mode.