FPGA based efficient DTMF detection using Split Goertzel algorithm with optimized resource sharing approach

Abstract

Dual-tone multi-frequency (DTMF) is a signaling standard in telecom applications that produces two tones simultaneously for each key press. The DTMF tones are chosen such that decoding the pressed key from the received tones is very easier. The DTMF tone detection is very crucial block in several telecom based embedded systems. As the current generation embedded systems are looking for key feature of low power, the DTMF detection algorithm also must be implemented with low power schemes. The DTMF detection is done with FFT based technique but which is power consuming type and it requires more hardware. In this project the FPGA based DTMF detection with very low power and low area using Split Goertzel algorithm is implemented in VHDL. The split Goertzel algorithm itself is an area optimized solution in comparison with the FFT, but in this project we initiate efforts to further makes it low power by building lot of serialism in the design. Since DTMF based applications don't require high speed tone detection the resource sharing approach can be used. In this approach very minimal set of hardware is scheduled as inputs and outputs at appropriate clock edges, for implementing the algorithm. In the first phase of the project we implemented FFT based DTMF detection using Xilinx FFT core. The area, timing and power results is analyzed. In the second phase the split Goertzel algorithm is implemented and analysis is carried out. In the next phase the resource sharing approach is studied and suitable state machine based scheduling will be carried with limited resources to implement split Goertzel algorithm. It will be demonstrated that the novel resource sharing based approach consumes less power and can still efficiently detect the DTMF tones. To test the project at various stage DTMF tone generator module also will be implemented with digital carrier generators. Mentor Graphics Modelsim Xilinx Edition (MXE) and Xilinx ISE is used for simulation and synthesis respectively. The Xilinx Chipscope tool is used to test the FPGA inside results while the logic running on FPGA. The Xilinx Spartan 3e FPGA Family board is used in this project.