FPGA based design of a fine-grained fault tolerant interleaved memory

Abstract

Memory bandwidth has been the bottleneck of modern computing systems with the advent of increasing processor speed. High speed processors engage themselves dealing data access with comparatively low speed memories resulting poor processor utilizing. Development of a high speed memory system is therefore a challenging domain of research. The concept of interleaved memory systems with high throughput plays a pivotal role in bridging the speed gap between processor and memory. Exploiting fault tolerance within an interleaved memory system makes it functionally more reliable with a trade-off in speed. Word level bypassing of the fault location is a fine grained approach of fault tolerance that can reduce wastage of significant amount of address space. FPGA based design and implementation of such a fault tolerant interleaved memory is proposed in this paper.